This invention relates to the design and testing of integrated circuits particularly large scale, application specific integrated circuits such as may be employed, for example, in high speed switching devices adapted to receive and transmit addressed data packets.
The design and layout of such integrated circuits (xe2x80x98chipsxe2x80x99) for use in the processing of digital signals is lengthy and complex. An important stage in the process from design to manufacture is a xe2x80x98de-buggingxe2x80x99 stage for the identification and correction of faults which need not necessarily arise from the high level design but which may arise owing to the infringements of limits on set up and hold times or other physical-level problems. Examples include paths with strict timing tolerance or xe2x80x98criticalxe2x80x99 paths within ASICs. In such examples small process variations or inaccuracies in simulation may produce intermittent faults.
When intermittent faults are identified in an ASIC during design verification testing it can be very difficult to isolate the faults to a specific block in the circuit. It is known to provide monitoring connections, usually called visibility buses, from internal nodes at key places in the data path but it is not always possible to select the correct paths to bring out the visibility buses to externally accessible pins.
One approach to the analysis of intermittent faults is to investigate temperature/voltage sensitivity, which can identify timing-related problems which may occur too sporadically or intermittently for certain identification of the location and cause of the fault. Generally such faults will increase in frequency as the local temperature increases. Heat guns, freezer spray or environmental changes have been proposed to vary the temperature but it is difficult to produce sufficiently specific local heating to obtain useful assistance in the isolation of faults.
The present invention envisages additional features within the ASIC to assist in the discovery of faults. The invention is based on the provision of power hungry modules, for example CRC (cyclic redundancy code) generators at various places on the chip and the individual enabling of such modules under selective control, for example by means of a CPU. Such modules may be inserted during the final placement of blocks in an ASIC technology using any one of the many computerised floor planning tools which are commercially available.
During design verification testing various heater modules could be enabled while running stress tests in order to identify potential design weaknesses as early as possible in the development stage. If intermittent faults do occur, these modules may be selectively enabled in different stages of the data path to help indicate regions on which attention may be focused.
Further features of the invention will be apparent from the accompanying drawings.